This application incorporates by reference Taiwanese application Ser. No. 88105564, filed Apr. 8, 1999.
1. Field of the Invention
The invention relates in general to a signal-decoding device and a decoding method, and more particularly to a device and method for deinterleaving data stored on disks.
2. Description of the Related Art
It is sometimes possible that a compact disk (CD) may suffer from physical damage, for example, scratches, during production or use. To prevent logical continuous data from being lost as a result of the physical damage, a data scramble technique is typically employed during the data-write process of CD read-only-memory (CD-ROM) production. In short, each logical continuous data stream is first divided into a plurality of blocks according to a predetermined algorithm. Afterwards, another algorithm is employed to scramble blocks of one logical continuous data stream with blocks of other logical continuous data streams. The resulting scrambled data are then sequentially and continuously written into the physical spaces of the CD-ROM. When, unfortunately, a certain portion of the CD-ROM is damaged, the portion of damaged data belonging to one logical continuous data stream may be recovered by the associated un-damaged data of the respective logical continuous data stream via the algorithm. Therefore, in addition to the raw data, some extra data, including control code, sync code, and protection code are added to the raw data to form the complete data in the CD-ROM.
In order to prevent data damage or loss, when original data are to be stored in disks, the following encoding operations are sequentially performed: C3 encoding, C2 encoding, interleaving, and C1 encoding.
The interleaving operation repartitions frames of C2 coded data into different frames for C1 coding. After interleaving, if data is damaged, the damaged data is dispersed among different frames of the decoded data, and thus correction probability is enhanced.
Therefore, when data in a disk is read, the following decoding operations are sequentially performed: C1 decoding, deinterleaving, C2 decoding, and C3 decoding. Deinterleaving is a reverse operation of interleaving.
Referring to FIG. 1, which shows a conventional deinterleaving operation. Each frame of C1 coded data includes 32 bytes, in which there are 4 bytes of parity check. After C1 coded data is parity-checked by the 4 parity bytes, 28 bytes of parity-checked C1 coded data are obtained.
As shown, in FIG. 1, a first byte (byte 0) of the parity-checked C1 coded data is delayed for 27xc3x974=108 cycles and then provided to a C2 decoder. A cycle represents a transmission unit of a frame. Similarly, a second byte (byte 1) of the parity-checked C1 coded data is delayed for 26xc3x974=104 cycles and then provided to the C2 decoder. Byte 2 of the parity-checked C1 coded data is delayed for 25xc3x974=100 cycles and then provided to the C2 decoder. The relation is summarized as follows: byte k is delayed for (27xe2x88x92k)xc3x974 cycles and then provided to the C2 decoder. Thus, byte 27 of the parity-checked C1 coded data is delayed for 0xc3x974=0 cycles and then provided to the C2 decoder
Each byte of the parity-checked C1 coded data is transmitted to the C2 decorder in pipeline mode. Between each byte received by the C2 decoder, there is a 4-frame transmission cycle delay.
That is to say, byte 0 of a first C2 frame received by the C2 decoder comes from byte 0 of the first C1 frame. Byte 1 of the first C2 frame comes from byte 1 of a fifth C1 frame. Byte 2 of the first C2 frame comes from byte 2 of a ninth C1 frame.
A symbol xe2x80x9cDxe2x80x9d in FIG. 1 represents delay registers. Each delay register is used to delay bytes of the C1 frame for one cycle. That is to say, in FIG. 1, there are 108, 104, . . . , 4, 0 delay registers used for delaying bytes 0, 1, . . . 27 of the C1 and C2 coders.
However, a disadvantage of this conventional scheme is that it uses a large number of delay registers. As shown in FIG. 1, it is clear that such a conventional system requires 108+104+ . . . +4+0=1512 delay registers to implement the deinterleaving process. The number of logic gates used for implementing so many delay registers is 44 k in total.
Therefore, according to the conventional system, a deinterleaving device is very complicated because 44 k logic gates are used. Circuit designers must take a great deal of time to design and debug such a system. The total cost for providing this large number of gates and testing the final design is high.
It is therefore an object of the invention to provide an improved and simplified device and method for deinterleaving data, for example during signal-decoding. By applying the present invention, the hardware cost can be reduced, and the circuit designer can design and debug the circuit more easily.
The invention achieves the above-identified objects by providing a method of deinterleaving bytes of a framed input signal to provide a deinterleaved framed output signal. The method includes: generating a write address A1; receiving sequential bytes of the input signal; storing the received bytes as write data according to the write address A1; generating a read address A2; and producing the output signal as sequential bytes of read data according to the read address A2. Generating a write address A1 includes: setting initial values of input parameters which correspond to characteristics of a current received byte; generating an initial write address based on the initial values of the input parameters; changing the values of ones of the input parameters to correspond to a next received byte; and repeatedly generating the write address A1 based on the changed values of the input parameters. Storing the received bytes as write data includes sequentially writing each of the received bytes to a respective memory address corresponding to the write address A1. Generating a read address A2 includes: setting initial value of output parameter which corresponds to characteristics of a current byte of read data; generating an initial read address based on the initial value of the output parameter; changing the value of the output parameter after each byte of read data is provided; and repeatedly generating the read address A2 based on the changed value of the output parameter. Providing the output signal as bytes of read data includes reading sequential bytes of the read data from a memory address corresponding to the read address A2. The invention is particularly applicable where the input signal is a parity-checked C1-coded signal having a 28-byte frame, and the output signal is a C2-coded signal having a 28-byte frame.
Preferably, the input parameters include a first input parameter I1, a second input parameter K1, and a third input parameter D. The first input parameter I1 corresponds to a frame identification of a current received byte. The second input parameter K1 corresponds to a byte identification of the current received byte. The third input parameter D corresponds to a delay identification of the current received byte. Likewise, the output parameters preferably include a output parameter I2. The output parameter I2 corresponds to a frame identification of a current byte of read data. Accordingly, an initial value of the first input parameter I1 corresponds to the number of frames in the input signal. An initial value of the second input parameter K1 corresponds to the first byte of the input signal. An initial value of the third input parameter D corresponds to an initial interleave delay between bytes in a frame of the input signal.
Further, changing the values of ones of the input parameters to correspond to a next received byte includes changing the parameters such that K1=K1+1 and D=D+N if K1 less than B.
The xe2x80x9cNxe2x80x9d corresponds to a number of clock cycle interleave delay units between bytes of the input signal. The xe2x80x9cBxe2x80x9d corresponds to a number of bytes in a frame of the input signal. When K1=B, the parameters I1, K1 and D are then changed. The first input parameter I1 is incremented. The second input parameter K1 is reset to its initial value. The third input parameter D is reset to its initial value.
Likewise, an initial value of the first output parameter I2 corresponds to a number that is 1 greater than the number of frames in the output signal. Generating the read address A2 includes accessing a memory location corresponding to A2=I2*Bxe2x88x921, wherein B corresponds to a number of bytes in a frame of the output signal. Changing the value of the output parameters to correspond to a next byte of read data includes changing the parameter such that I2=I2+1.
A method of deinterleaving bytes of a framed input signal to provide a deinterleaved framed output signal according to a particular preferred embodiment includes: generating a write address A1; storing the input signal as bytes of write data according to the write address A1; generating a read address A2; and providing the output signal as bytes of read data according to the read address A2. The write address A1 corresponds to three parameters-an input frame parameter I1, an input byte parameter K1, and a row difference parameter D. These three parameters have their own initial values. After each byte of write data is stored, the values of ones of the input frame parameter I1, the input byte parameter K1, and the row difference parameter D are changed. The write address A1 are repeatedly generated based on the changed values of the input frame parameter I1, the input byte parameter K1, and the row difference parameter D. Storing the input signal as bytes of write data includes writing sequential bytes of the input signal to a memory address corresponding to the write address A1. The read address A2 has an initial value. An initial read address A2 is generated based on the initial value of the output frame parameter I2. After each byte of read data is provided, the value of the output frame parameter I2 is changed. The read address A2 is repeatedly generated based on the changed value of the output frame parameter I2. Providing the output signal as bytes of read data includes reading sequential bytes of the read data from a memory address corresponding to the read address A2. The invention is particularly applicable where the input signal is a parity-checked C1-coded signal having a 28-byte frame, and the output signal is a C2-coded signal having a 28-byte frame. Writing sequential bytes of the input signal to a memory address includes writing to an array memory, which is preferably a 4Kbyte SRAM. Preferably, the initial value of the input frame parameter I1 is 108, the initial value of the row difference parameter D is 0, and the initial value of the input byte parameter K1 is 0.
Further, changing the values of ones of the input parameters to correspond to a next received byte includes changing the parameters such that K1=K1+1 and D=D+4 if K1 less than 28. When K1=28, the parameters I1, K1 and D are then changed. The first input parameter I1 is incremented by 1. The second input parameter K1 is reset to its initial value. The third input parameter D is reset to its initial value.
Likewise, an initial value of the first output parameter I2 corresponds to a number that is 1 greater than the number of frames in the output signal. Generating the read address A2 includes accessing a memory location corresponding to A2=I2*Bxe2x88x921, wherein B corresponds to a number of bytes in a frame of the output signal. Changing the value of the output parameters to correspond to a next byte of read data includes changing the parameter such that I2=I2+1.
A decoding device for deinterleaving bytes of framed input data according to the invention includes a memory device that stores the input data and provides output data, a write address generator that generates a write address A1 for writing the input data to the memory device, wherein the write address A1 is based on an input frame parameter I1, and a read address generator that generates a read address A2 for reading the output data from the memory device, wherein the read address A2 is based on an output frame parameter I2. The device has particular advantageous applicability when the input data stored in the memory is a parity-checked C1-coded signal having a 28-byte frame, and the output data provided by the memory is a C2-coded signal having a 28-byte frame. Preferably, the memory device is a 4Kbyte SRAM having addresses arranged in an array. The write address A1 is further based on an input byte parameter K1 and a row difference parameter D. An initial write address is based on an initial input frame parameter I1=108, an initial input byte parameter K1=0, and an initial row difference parameter D=0. The write address A1 generated by the write address generator is expressed by A1=(I1xe2x88x92D)*28+K1. Likewise, an initial read address is based on an initial output frame parameter I2=109. The read address A2 is further based on the read address A2 generated by the read address generator is expressed by A2=I2*28xe2x88x921.